A floating-gate transistor is mainly used in a flash to store information. Compared with a normal MOSFET, a floating gate is added to the gate electrode structure of the floating-gate transistor. The threshold voltage of the device is different when charge is stored in the floating gate from when the charge is not stored. Consequently, the floating-gate transistor remains in different status. For N-type devices, the threshold voltage thereof may increase after charges are written into (i.e., programmed into) the floating gate, and the channel is cut off when voltage is not applied to the control gate; the threshold voltage thereof may decrease after charges are erased from the floating gate, and the channel is turned on when voltage is not applied to the control gate.
Normally, a memory cell is composed of a floating-gate transistor. Multiple memory cells are arranged into array structures thereby forming flash arrays. Memory cells in the flash array are linked to their corresponding word lines, bit lines and source lines. When signals are added to respective word lines and bit lines in accordance with relevant address signals, the related memory cells can be selected, thereby performing Read, Erase and Program operations for the selected memory cells.
While reading memory cells, it is necessary to extract currents from respective bit lines and to judge the status of memory cells by comparing the bit line current with the reference current. For instance, when a memory cell is in an Erase status, the channel thereof is turned on, so that it is possible to extract current larger than reference current from corresponding bit line; when a memory cell is in a Program status, the channel thereof is cut off, in this way, the current extracted from corresponding bit lines will be smaller than the reference current.
Therefore, the reference current plays the role of a benchmark in the reading process of a memory cell, and it is necessary for the reference current to correctly reflect the status of the memory cell. FIG. 1 is a reference-current generation circuit for flash, which is independent from the flash array, therefore, the structure of the flash array is not shown in FIG. 1. The reference-current generation circuit 101 is composed of a number of reference cells 102 being arranged into an array of columns and rows. The reference cell 102 usually has the same structure as the memory cell and both of them are formed simultaneously by the same process. The reference-current generation circuit array 101 in FIG. 1 is composed of m rows and n columns. All the reference cells 102 of the same row are linked by the same word line. All the word lines are represented by WL0, WL1, WL2 until WLm respectively, of which “WL” stands for a word line and the number immediately after the “WL” represents the number of the respective row; all the reference cells 102 of the same column are linked by the same bit line. In order to differentiate these bit lines from the bit lines in memory cells, the bit lines in FIG. 1 are what provide references for the bit lines in memory cells, and therefore are also called reference bit lines. So all the reference bit lines in FIG. 1 are represented by RefBL0, RefBL1, RefBL2 until RefBLn respectively, of which “RefBL” stands for a reference bit line and the number immediately after the “RefBL” represents the number of the respective column. As shown in FIG. 1, reference currents are provided by the reference bit lines of the columns, and they are represented by Iref0, Iref1, Iref2 until Irefn respectively.
All the reference cells 102 in FIG. 1 adopt a status of Erase, that is to say, various reference cells 102 will not be programmed. The reference current finally provided is the average value of the currents of various reference bit lines multiplied by a corresponding proportional coefficient, which can be represented by the following formula (1):
                              Iref          =                                    x                              n                +                1                                      ×                                          ∑                                  i                  =                                      0                    ⁢                    …                    ⁢                                                                                  ⁢                    n                                                                                                                ⁢              Irefi                                      ;                            (        1        )            
wherein, “Iref” represents the reference current finally provided by the reference-current generation circuit 101; “n” represents the maximum of the column numbers; “i” stands for the column number with which each summation item corresponds; “Irefi” represents the current of the reference bit line for column i.
In general, a reference cell 102 is the same as a memory cell, and the reference cell 102 is in Erasure status. In other words, the reference current is obtained via the memory cell having undergone a saturated erasure. Since the reference cell 102 remains in an erased status but the memory cell in the flash array may be erased repeatedly in the course of usage, the memory cell in the flash array may vary with work processes, voltages and temperature, etc., while the reference cell 102 obviously cannot track these changes of the memory cells in the flash array. Thus, the reference cell 102 has a feature that the I_V and temperature of the reference cells are unable to track the changes of the memory cells, i.e., the characteristic of track tail bit, thus affecting the velocity and precision of the sensitive amplifier as well as the yield and performance of the flash as a whole.